Field of the Invention
The invention relates to a delay locked loop in which a delay device with a controllable delay time is connected between an input terminal for obtaining a signal to be delayed and an output terminal for providing a delayed signal. The delay time is set in a manner dependent on a phase difference between the input signal and the output signal.
Delay locked loops are used to delay an input clock signal using a control loop in such a way that the output signal has a predetermined phase angle. By way of example, such delay locked loops are provided in clock-controlled integrated circuits, for example, in synchronously operated dynamic semiconductor memories that operate according to double data rate principle DDR SDRAMs (Double Data Rate Synchronous Dynamic Random Access Memories). In that case, the data values that are read out are provided synchronously with a clock signal fed in to the input — to be precise both on the rising and on the falling edge of the clock signal. The phase locked loop takes account of the internal signal propagation times of the fed in clock signal and supplies the output driver with a suitably delayed clock signal in order to output the output data again synchronously with the clock signal present on the external data bus.
A delay locked loop (DLL) in a DDR SDRAM should have a low power loss, particularly in standby operation, and must be operable in a large operating frequency range. A low operating frequency requires that the delay device, contained in the control loop, have a long controllable delay time. Present-day concepts for a delay locked loop therefore provide a two-stage delay device, namely a delay device for the coarse setting of the delay time and a further, series-connected delay device for the fine setting of the delay time. FIG. 3 of published German Patent Application DE 199 30 167 describes a delay locked loop having two delay devices for the coarse setting of the delay time and for the fine setting of the delay time. The delay devices are connected in series with regard to the clock signal to be delayed. The delay device with the coarse setting is connected first in the signal path, and the delay device with the fine setting of the delay time is connected downstream. The control signals for setting the delay time, which are fed to the two delay devices, are provided in an appropriately timed manner to the delay devices by a storage element serving for synchronization, a so-called synchronization latch. The synchronization latch assigned to the coarse delay device is controlled by the output signal of this coarse delay device, and the synchronization latch assigned to the fine delay device is controlled by the output signal of the fine delay device. In addition, a further synchronization latch is connected upstream of the last-mentioned synchronization latch. The delay locked loop has the disadvantage of having a small control bandwidth on account of the long signal path from the control device to the fine delay unit via the two synchronization latches.